1. Field of the Invention
The present invention relates generally to a voltage-to-current converter, and more specifically, to compensating variations in an output current of a voltage-to-current converter caused by process-voltage-temperature (PVT) variations.
2. Description of the Related Art
A phase-locked loop (PLL) is a closed-loop feedback control system that generates and outputs a signal in relation to the frequency and phase of an input reference signal. A PLL responds to both the frequency and the phase of the input reference signal, automatically raising or lowering the frequency of a controlled oscillator until it matches the input reference signal in both frequency and phase.
FIG. 1 shows a schematic block diagram of a conventional PLL. A PLL generally includes a phase/frequency detector (PFD) 102, a charge pump 104, a low pass filter 106, a voltage-controlled oscillator (VCO) 112, and a feedback divider 114. The PFD 102 compares the phase of the feedback signal FFB from the feedback divider 114 with a reference signal FIN and generates an error signal. If the phase of FFB lags that of FIN, the PFD 102 causes the charge pump 104 to increase the control voltage so that the VCO 112 speeds up. Likewise, if the phase of FFB creeps ahead of that of FIN, the PFD 102 causes the charge pump 104 to lower the control voltage to slow down the VCO 112. The low pass filter 106 smoothes out the abrupt changes in control inputs from the charge pump 104.
A typical VCO 112 includes a voltage-to-current converter 108 and a current-controlled oscillator (ICO) 110. The voltage-to-current converter 108 converts a voltage signal from the low pass filter 106 to a current signal. The current signal is then provided to the ICO 110 to generate an output signal Fout.
FIG. 2 shows a circuit diagram of a conventional voltage-to-current converter 108. The voltage-to-current converter 108 includes a field effect transistor (FET) 202, an input 204, an output 206, and a resistor R. The input 204 of the voltage-to-current converter 108 is coupled to the gate of the FET 202 to receive the control voltage VC1. The output 206 of the voltage-to-current converter 108 is coupled to the ICO 110. One end of the resistor R is coupled to the source of the FET 202 and the other end of the resistor R is grounded. The voltage-to-current converter 108 controls a current IICO1 from the ICO 110 based on the control voltage VC1.
The voltage-to-current converter 108 of FIG. 2, however, does not provide compensation for process-voltage-temperature (PVT) variations in the threshold voltage of the FET 202. Accordingly, the PVT variations of the threshold voltage of the FET 202 may cause jitters in the current IICO1. Such jitters cause the voltage-to-current converter to be less accurate and reliable than desired. The inaccuracy and unreliability of the voltage-to-current converter in turn results in overall degraded performance of the PLL because of the jitters in the output signal Fout.
Another disadvantage of the voltage-to-current converter 108 of FIG. 2 is that the current IICO1 is completely cut off when the control voltage VC1 is below the threshold voltage of the FET 202. Therefore, the ICO 110 will stop generating signals when the control voltage VC1 falls below the threshold voltage of the FET 202. This is problematic because digital systems receiving the signals from the ICO 110 will malfunction when the signals are not received from the ICO 110. Therefore, the digital systems with the ICO 110 are more vulnerable to malfunctioning compared to the digital systems that do not use ICO 110.
Therefore, there is a need for a voltage-to-current converter that can compensate for PVT variations of the threshold voltage of the FET. There is also a need for a voltage-to-current converter that provides a minimum current to an ICO even when the control voltage is below the threshold voltage of the FET.